Generally, in order to read out data from a memory cell, the data in the memory cell are induced on a bit line by the activation of a word line and a bit line sense amplifier is driven to amplify the induced voltage on the bit line. Thereafter, it is required to restore the amplified cell voltage on the bit line to the memory cell. When a write operation is driven in order to store data from an external circuit in a memory cell, an inverted or a non-inverted voltage of an amplified voltage on the bit line is stored in the memory cell. A memory operation section, in which this amplified voltage level on bit line is stored in the memory cell, may be one of a restore section and a write section.
Referring to FIG. 1, a memory cell 110 is coupled to both a bit line BL and a word line WL and a sense amplifier 120 is coupled to a pair of bit lines BL and /BL. The word line WL is driven by a row decoder/word line driver 140. A specific word line is activated in response to a word line control signal WL_crt, which is activated by an active command, and to a decoding signal which is produced by row address signals row_add. Since a cell access transistor is an NMOS transistor and a threshold voltage Vt is applied to the bit line when a bit line potential is transferred to the cell, the voltage loss of the threshold voltage is caused. In order to compensate for this threshold voltage loss, a high voltage level Vpp is applied to the word line and a high voltage generator 130 is provided to generate such a high voltage level Vpp which is higher than an external voltage level of the memory. A driving voltage generator 160 is enabled by enable signals rtoen and sben which are activated in a sense amplifier controller (not shown) and driving voltage signals RTO and SB are transferred to the bit line sense amplifier 120.
FIG. 2A is a waveform illustrating a restore operation in case that a logic high data (H) is stored in the cell. A high voltage level Vpp for the word line is activated by an active command (that is, row active signal rowact is activated) and a cell data is induced on the bit line BL by the charge sharing when the access transistor is turned on by the activated word line WL. Namely, the potential on the bit line BL is increased a little and that of the bit line /BL is kept in a precharge level Vdd/2. As a result, a voltage difference ΔV between the bit lines BL and /BL is caused by the data voltage stored in the cell (section A in FIG. 2A).
After a predetermined sensing margin time, if the enable signals rtoen and sben are enabled through the sense amplifier controller, the driving voltage generator 160 and the sense amplifier 120 are driven so that the fine voltage (ΔV) is amplified. Accordingly, the voltage level of the bit line BL goes to the voltage level Vdd and that of the bit line /BL goes to the ground voltage level GND (section B in FIG. 2A).
Although the bit lines BL and /BL are completely amplified up to the voltage level Vdd and the ground voltage level GND, respectively, the word line WL should be continuously activated by the restore operation because these amplified voltage levels are restored in the memory cell (section C in FIG. 2A).
After the complete of restore operation, the word line is non-activated by the precharge command and the bit lines BL and /BL are precharged with the removal of the fine voltage difference (section D in FIG. 2A).
FIG. 2B is a waveform illustrating a write operation in case that a logic high data (H) is written in the memory cell.
The high voltage level Vpp for the word line is activated by an active command (that is, row active signal rowact is activated) and cell data is induced on the bit line BL by the charge sharing when the access transistor is turned on by the activated word line WL. Namely, the potential on the bit line BL is increased a little and that of the bit line /BL is kept in a precharge level Vdd/2. As a result, a voltage difference ΔV between the bit lines BL and /BL is caused by the data voltage stored in the cell (section A in FIG. 2B).
After a predetermined sensing margin time, if the enable signals rtoen and sben are enabled through the sense amplifier controller, the driving voltage generator 160 and the sense amplifier 120 are driven so that the voltage difference (ΔV) is amplified. Accordingly, the voltage level of the bit line BL goes to the voltage level Vdd and that of the bit line /BL goes to the ground voltage level GND (section B in FIG. 2B).
A high voltage level “H” is applied to the bit line BL through a write driver (not shown in FIG. 1) in response to the write command so that an inversion of the high voltage level occurs on the bit lines BL and /BL and, since the word line is activated, the cell voltage is in compliance with the potential variation of the bit line (section C in FIG. 2B).
Finally, after the writing operation has been completed, the word line is non-activated by the precharge command and the bit lines BL and /BL are precharged to the same voltage level.
Referring to sections C in the FIGS. 2A and 2B in which the bit line voltage is applied to the memory cell, the cell voltage stored in the memory cell is lower than the bit line voltage so that the logic high voltage “H” stored in the memory cell is not sufficient to guarantee the reliability of the cell data. The reason why the cell voltage stored in the memory cell is lower than the bit line voltage is that the high voltage level Vpp using an external voltage Vext is relatively low and the high voltage level Vpp on the word line does not overcome the threshold voltage Vt of the access transistor. Further, with the increase of the circuit integration, this problem can be caused by the decrease of an internal operation voltage. That is, since a contact fabricating process is getting hard in the highly integrated circuit design, the size of the access transistor is getting smaller and a contact resistance is getting higher. Although the external voltage drop is not generated, the high voltage transfer cannot be normally carried out if there is a problem in the contact process. As a result, the contact problem in the fabrication process makes the cell voltage drop as the same as the external voltage drop.
As stated above, in the conventional memory device, both the contact problem in the fabrication process and the external voltage drop make the voltage drop in the memory cell. This cell voltage drop, which obstructs the reliability of the cell data, occurs irrespective of the precharge voltage level.